The down scaling of semiconductor device structures, such as, for example, complementary metal-oxide-semiconductor (CMOS) devices, has led to significant improvements in speed and density of integrated circuits. However, conventional device scaling faces immense challenges for future technology nodes.
In the field of semiconductor device fabrication, the trend is towards a reduction in the deposition temperature of the useful layers comprising the semiconductor device, such as, for example, metal-containing layers, dielectric layers, and semiconductor layers. A reduction in the deposition temperature of useful layers may be desirable due to decreasing thermal budget requirements often necessary for the fabrication of state of the art semiconductor device structures, such as, for example, complementary metal-oxide-semiconductor (CMOS) device structures, and dynamic random access memory (DRAM) device structures. In particular semiconductor fabrication processes, high temperature deposition of useful layers may result in the unwanted thermal diffusion of materials into undesirable areas of the device structure as well as the formation of unwanted materials.
A number of semiconductor device structures may require one or more silicon layers, preferably deposited at a low deposition temperature. However, the low temperature deposition of silicon layers, e.g., below a deposition temperature of approximately 550° C., may result in silicon layers with an amorphous structure. In some semiconductor device applications, the polycrystalline form of silicon is more desirable, such as, for example, as a polycrystalline channel region of a semiconductor device structure. Accordingly, methods are desirable for enabling the low temperature deposition of polycrystalline silicon materials and particularly for the low temperature deposition of polycrystalline silicon material with p-type conductivity.